| * |
VDD : 2.3V ~ 2.7V, VDDQ : 2.3V ~ 2.7V for DDR266/333. |
| * |
VDD : 2.5V ~ 2.7V, VDDQ : 2.5V ~ 2.7V for DDR400. |
| * |
Double-data-rate architecture; two data transfers per clock cycle. |
| * |
Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16). |
| * |
Differential clock inputs(CK and /CK). |
| * |
DLL aligns DQ and DQS transition with CK transition. |
| * |
Programmable Read latency 2, 2.5 (clock) for DDR266/333. |
| * |
Programmable Read latency 2.5,3 (clock) for DDR400. |
| * |
Programmable Burst length (2, 4, 8). |
| * |
Programmable Burst type (sequential & interleave). |
| * |
Edge aligned data output, center aligned data input. |
| * |
Auto & Self refresh, 7.8 us refresh interval(8K/64ms refresh). |
| * |
Serial presence detect with EEPROM. |
| * |
PCB : Height 1,250 (mil) & single (256, 512MB), double (1GB) sided. |
| * |
SSTL_2 Interface. |
