DDRII 667
 

Feature
Capacity:

  Feature
* JEDEC standard 1.8V¡Ó 0.1V Power Supply.
* VDDQ = 1.8V¡Ó 0.1V
* 267MHz fCK for 533Mb/sec/pin, 333MHz fCKfor 667Mb/sec/pin,400MHz fCK for 800Mb/sec/pin
* 4 Banks
* Posted /CAS
* Programmable /CAS Latency: 4,5.
* Programmable Additive Latency: 0, 1 , 2 , 3 and 4.
* Write Latency(WL) = Read Latency(RL) -1.
* Burst Length : 4 , 8(Interleave/nibble sequential).
* Programmable Sequential / Interleave Burst Mode.
* Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature).
* Off-Chip Driver(OCD) Impedance Adjustment.
* On Die Termination with selectable values(50/75/150 ohms or disable).
* PASR(Partial Array Self Refresh).
* Average Refresh Period 7.8us at lower than a TCASE 85¢XC, 3.9us at 85¢XC < TCASE ?z 95¢XC.
  - support High Temperature Self-Refresh rate enable feature.
* All of Lead-free products are compliant for RoHS.

 


¡@Capacity:

Density (Mbytes) Organization Speed Component Composition
256 32M * 64 PC4200 / 5300 32M * 8 * 8ea
256 32M * 64 PC4200 / 5300 32M * 16 * 4ea
512 64M * 64 PC4200 / 5300 32M * 8 * 16ea
512 64M * 64 PC4200 / 5300 32M *16 * 8ea
512 64M * 64 PC4200 / 5300 64M * 8 * 8ea
1024 128M * 64 PC4200 / 5300 64M * 8 * 16ea