| * |
Burst mode operation. |
| * |
Auto & self refresh capability (8192 Cycles/64ms). |
| * |
LVTTL compatible inputs and outputs. |
| * |
Single power supply of 3.3V¡Ó0.3V power supply. |
| * |
DMRS cycle with address key programs Latency (Access from column address). |
| * |
Burst length (1, 2, 4, 8 & Full page). |
| * |
Data scramble (Sequential & Interleave). |
| * |
All inputs are sampled at the positive going edge of the system clock. |
| * |
Serial presence detect with EEPROM. |
