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JEDEC standard 1.5V ¡Ó 0.075V Power Supply |
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V DDQ = 1.5V ¡Ó 0.075V |
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533MHz f CK for 1066Mb/sec/pin, 667MHz f CK for 1333Mb/sec/pin |
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8 independent internal bank |
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Programmable CAS Latency: 6,7,8,9,10 |
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Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock |
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Programmable CAS Write Latency(CWL) = 6(DDR3-1066) and 7(DDR3-1333) |
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8-bit pre-fetch |
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Burst Length: 8 (Interleave without any limit, sequential with starting address ¡§ 000¡¨ only), 4 with tCCD = 4 which does not allow seamless read orwrite [either On the fly using A12 or MRS] |
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Bi-directional Differential Data Strobe |
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Internal(self) calibration :
Internal self calibration through ZQ pin (RZQ : 240 ohm ¡Ó1%) |
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On Die Termination using ODT pin |
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Average Refresh Period 7.8us at lower then T CASE 85 ¢X C ,
3.9us at 85 ¢X C < T CASE 95 ¢X C |
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Asynchronous Reset |
