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2.6V¡Ó0.1V power supply |
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Double-data-rate architecture; two data transfers per clock cycle. |
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Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16). |
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Differential clock inputs(CK and /CK). |
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DLL aligns DQ and DQS transition with CK transition. |
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Programmable Read latency 2.5,3 (clock) for DDR400. |
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Programmable Burst length (2, 4, 8). |
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Programmable Burst type (sequential & interleave). |
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Edge aligned data output, center aligned data input. |
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Auto & Self refresh, 7.8 us refresh interval(8K/64ms refresh). |
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Serial presence detect with EEPROM. |
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PCB : Height 1,250 (mil) & single (256, 512MB), double (1GB) sided. |
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SSTL_2 Interface. |
